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HYNIX SEMICONDUCTOR INC. 8-BIT SINGLE-CHIP MICROCONTROLLERS
GMS90C3X GMS90C5X GMS97C5X
User's Manual (Ver. 3.1a)
Version 3.1a Published by MCU Application Team (c)2001 Hynix semiconductor All right reserved.
Additional information of this manual may be served by Hynix semiconductor offices in Korea or Distributors and Representatives listed at address directory. Hynix semiconductor reserves the right to make changes to any information here in at any time without notice. The information, diagrams and other data in this manual are correct and reliable; however, Hynix semiconductor is in no way responsible for any violations of patents or other rights of the third party generated by the use of this manual.
GMS90 Series
Device Naming Structure
GMS90X5X - GBXXX XX XX
Frequency Blank: 12MHz 16: 16MHz 24: 24MHz 40: 40MHz Package Type Blank: 40PDIP PL: 44PLCC Q: 44MQFP ROM Code serial No. ROM size 1: 4k bytes 2: 8k bytes 4: 16k bytes 6: 24k bytes 8: 32k bytes Operating Voltage C: 4.25~5.5V L: 2.7~3.6V
GMS97X5X X XX
Package Type Blank: 40PDIP PL: 44PLCC Q: 44MQFP Frequency Blank: 12/24(5V),12MHz(3V) H: 33MHz ROM size 1: 4k bytes 2: 8k bytes 4: 16k bytes 6: 24k bytes 8: 32k bytes Operating Voltage C: 4.25~5.5V L: 2.7~3.6V
Hynix semiconductor MCU Hynix semiconductor MCU
Oct. 2000 Ver 3.1a
OTP version
Mask ROM version
GMS90 Series
GMS90 Series Selection Guide
Operating Voltage (V) ROM size (bytes) MASK ROM-less 4K 8K 16K 24K 32K 4.25~5.5 4K 4K 8K 8K 16K 16K 24K 24K 32K 32K ROM-less 4K 8K 16K 24K 32K 4K 8K 16K 24K 32K OTP RAM size (bytes) 128 256 128 256 256 256 256 128 128 256 256 256 256 256 256 256 256 128 256 128 256 256 256 256 128 256 256 256 256 Device Name GMS90C31 GMS90C32 GMS90C51 GMS90C52 GMS90C54 GMS90C56 GMS90C58 GMS97C51 GMS97C51H GMS97C52 GMS97C52H GMS97C54 GMS97C54H GMS97C56 GMS97C56H GMS97C58 GMS97C58H GMS90L31 GMS90L32 GMS90L51 GMS90L52 GMS90L54 GMS90L56 GMS90L58 GMS97L51 GMS97L52 GMS97L54 GMS97L56 GMS97L58 Operating Frequency (MHz) 12/24/40 12/24/40 12/24/40 12/24/40 12/24/40 12/24/40 12/24/40 12/24 33 12/24 33 12/24 33 12/24 33 12/24 33 12/16 12/16 12/16 12/16 12/16 12/16 12/16 12 12 12 12 12
2.7~3.6
Oct. 2000 Ver 3.1a
GMS90 Series
GMS90C31/51, 97C51 GMS90L31/51, 97L51 (Low voltage versions)
* Fully compatible to standard MCS-51 microcontroller * Wide operating frequency up to 40MHz (for more detail, see "GMS90 Series Selection Guide") * 4K x 8 (EP)ROM * 128 x 8 RAM * 64K external program memory space * 64K external data memory space * Four 8-bit ports * Two 16-bit Timers / Counters * USART * Five interrupt sources, two priority levels * Power saving Idle and power down mode * Quick pulse programming algorithm (in the OTP devices) * 2-level program memory lock (in the OTP devices) * 2.7Volt low voltage version available * P-DIP-40, P-LCC-44, P-MQFP-44 package
Block Diagram
RAM 128 x 8 T0 CPU T1 ROM / EPROM 4K x 8 8-BIT USART
PORT 0
I/O
PORT 1
I/O I/O
PORT 2
PORT 3
I/O
Oct. 2000 Ver 3.1a
1
GMS90 Series
GMS90C32/52, 97C52 GMS90L32/52, 97L52 (Low voltage versions)
* Fully compatible to standard MCS-51 microcontroller * Wide operating frequency up to 40MHz (for more detail, see "GMS90 Series Selection Guide") * 8K x 8 (EP)ROM * 256 x 8 RAM * 64K external program memory space * 64K external data memory space * Four 8-bit ports * Three 16-bit Timers / Counters (Timer2 with up/down counter feature) * USART * Six interrupt sources, two priority levels * Power saving Idle and power down mode * Quick pulse programming algorithm (in the OTP devices) * 2-level program memory lock (in the OTP devices) * 2.7Volt low voltage version available * P-DIP-40, P-LCC-44, P-MQFP-44 package
Block Diagram
RAM 256 x 8 T0 T2 T1 ROM / EPROM 8K x 8 CPU 8-BIT USART
PORT 0
I/O
PORT 1
I/O I/O
PORT 2
PORT 3
I/O
2
Oct. 2000 Ver 3.1a
GMS90 Series
GMS90C54/56/58, 97C54/56/58 GMS90L54/56/58, 97L54/56/58 (Low voltage versions)
* Fully compatible to standard MCS-51 microcontroller * Wide operating frequency up to 40MHz (for more detail, see "GMS90 Series Selection Guide") * 16K/24K/32K bytes (EP)ROM * 256 x 8 RAM * 64K external program memory space * 64K external data memory space * Four 8-bit ports * Three 16-bit Timers / Counters (Timer2 with up/down counter feature) * USART * One clock output port * Programmable ALE pin enable / disable * Six interrupt sources, two priority levels * Power saving Idle and power down mode * Quick pulse programming algorithm (in the OTP devices) * 2-level program memory lock (in the OTP devices) * 2.7Volt low voltage version available * P-DIP-40, P-LCC-44, P-MQFP-44 package
Block Diagram
RAM 256 x 8 T0 T2 T1 ROM / EPROM GMS9XX54: 16K x 8 GMS9XX56: 24K x 8 GMS9XX58: 32K x 8 CPU 8-BIT USART
PORT 0
I/O
PORT 1
I/O I/O
PORT 2
PORT 3
I/O
Oct. 2000 Ver 3.1a
3
GMS90 Series
PIN CONFIGURATION
44-PLCC Pin Configuration (top view)
P1.1 / T2EX
P0.0 / AD0
P0.1 / AD1 42
P0.2 / AD2 41
P1.4
P1.3
P1.2
44
VCC
INDEX CORNER
43
40
6
5
4
3
2
1
P0.3 / AD3
P1.0 / T2
N.C.*
P1.5 P1.6 P1.7 RESET RxD / P3.0 N.C.* TxD / P3.1 INT0 / P3.2 INT1 / P3.3 T0 / P3.4 T1 / P3.5
7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
39 38 37 36 35 34 33 32 31 30 29
P0.4 / AD4 P0.5 / AD5 P0.6 / AD6 P0.7 / AD7 EA / VPP N.C.* ALE / PROG PSEN P2.7 / A15 P2.6 / A14 P2.5 / A13
XTAL2
XTAL1
N.C.*
P2.3 / A11
WR / P3.6
RD / P3.7
P2.0 / A8
P2.1 / A9
P2.2 / A10
N.C.: Do not connect.
4
P2.4 / A12
VSS
Oct. 2000 Ver 3.1a
GMS90 Series
40-PDIP Pin Configuration (top view)
T2 / P1.0 T2EX / P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 RESET RxD / P3.0 TxD / P3.1 INT0 / P3.2 INT1 / P3.3 T0 / P3.4 T1 / P3.5 WR / P3.6 RD / P3.7 XTAL2 XTAL1 VSS
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21
VCC P0.0 / AD0 P0.1 / AD1 P0.2 / AD2 P0.3 / AD3 P0.4 / AD4 P0.5 / AD5 P0.6 / AD6 P0.7 / AD7 EA / VPP ALE / PROG PSEN P2.7 / A15 P2.6 / A14 P2.5 / A13 P2.4 / A12 P2.3 / A11 P2.2 / A10 P2.1 / A9 P2.0 / A8
Oct. 2000 Ver 3.1a
5
GMS90 Series
44-MQFP Pin Configuration (top view)
P1.1 / T2EX
P0.0 / AD0
P0.1 / AD1 36
P0.2 / AD2 35
P1.0 / T2
N.C.*
P1.4
P1.3
P1.2
44
43
42
41
40
39
38
VCC
37
34
P0.3 / AD3
P1.5 P1.6 P1.7 RESET RxD / P3.0 N.C.* TxD / P3.1 INT0 / P3.2 INT1 / P3.3 T0 / P3.4 T1 / P3.5
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22
33 32 31 30 29 28 27 26 25 24 23
P0.4 / AD4 P0.5 / AD5 P0.6 / AD6 P0.7 / AD7 EA / VPP N.C.* ALE / PROG PSEN P2.7 / A15 P2.6 / A14 P2.5 / A13
XTAL2
XTAL1
P2.3 / A11
WR / P3.6
RD / P3.7
P2.0 / A8
P2.1 / A9
P2.2 / A10
N.C.: Do not connect.
6
P2.4 / A12
VSS
N.C.*
Oct. 2000 Ver 3.1a
GMS90 Series
Logic Symbol
VCC
VSS
XTAL1 XTAL2
Port 0 8-bit Digital I/O Port 1 8-bit Digital I/O Port 2 8-bit Digital I/O
RESET
EA/VPP ALE/PROG PSEN Port 3 8-bit Digital I/O
Oct. 2000 Ver 3.1a
7
GMS90 Series
PIN DEFINITIONS AND FUNCTIONS
Pin Number Symbol P1.0-P1.7
PLCC44 PDIP40 MQFP44
Input/ Output I/O
Function Port1 Port 1 is an 8-bit bidirectional I/O port with internal pull-ups. Port 1 pins that have 1s written to them are pulled high by the internal pull-up resistors and can be used as inputs. As inputs, port 1 pins that are externally pulled low will source current because of the pulls-ups (IIL, in the DC characteristics). Pins P1.0 and P1.1 also. Port1 also receives the low-order address byte during program memory verification. Port1 also serves alternate functions of Timer 2. P1.0 / T2 : Timer/counter 2 external count input P1.1 / T2EX : Timer/counter 2 trigger input In GMS9XC54/56/58: P1.0 / T2, Clock Out : Timer/counter 2 external count input, Clock Out
2-9
1-8
40-44, 1-3
2 3
1 2
40 41
2 P3.0-P3.7 11, 13-19
1 10-17
40 5, 7-13 I/O
Port 3 Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. Port 3 pins that have 1s written to them are pulled high by the internal pull-up resistors and can be used as inputs. As inputs, port 3 pins that are externally pulled low will source current because of the pulls-ups (IIL, in the DC characteristics). Port 3 also serves the special features of the 80C51 family, as listed below. P3.0 / RxD receiver data input (asynchronous) or data input output(synchronous) of serial interface 0 transmitter data output (asynchronous) or clock output (synchronous) of the serial interface 0 interrupt 0 input/timer 0 gate control interrupt 1 input/timer 1 gate control counter 0 input counter 1 input the write control signal latches the data byte from port 0 into the external data memory the read control signal enables the external data memory to port 0
11
10
5
13
11
7
P3.1 / TxD
14 15 16 17 18
12 13 14 15 16
8 9 10 11 12
P3.2 /INT0 P 3.3 / IN T 1 P3.4 /T0 P3.5 /T1 P3.6 / WR
19 XTAL2 20
17 18
13 14 O
P3.7 /RD
XTAL2 Output of the inverting oscillator amplifier.
8
Oct. 2000 Ver 3.1a
GMS90 Series
Pin Number Symbol XTAL1
PLCC44 PDIP40 MQFP44
Input/ Output I
Function XTAL1 Input to the inverting oscillator amplifier and input to the internal clock generator circuits.To drive the device from an external clock source, XTAL1 should be driven, while XTAL2 is left unconnected. There are no requirements on the duty cycle of the external clock signal, since the input to the internal clocking circuitry is divided down by a divide-by-two flip-flop. Minimum and maximum high and low times as well as rise fall times specified in the AC characteristics must be observed. Port 2 Port 2 is an 8-bit bidirectional I/O port with internal pull-ups. Port 2 pins that have 1s written to them are pulled high by the internal pull-up resistors and can be used as inputs. As inputs, port 2 pins that are externally pulled low will source current because of the pulls-ups (IIL, in the DC characteristics).Port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memory that use 16-bit addresses (MOVX @DPTR). In this application it uses strong internal pull-ups when emitting 1s. During accesses to external data memory that use 8-bit addresses (MOVX @Ri), port 2 emits the contents of the P2 special function register. The Program Store Enable The read strobe to external program memory when the device is executing code from the external program memory. PSEN is activated twice each machine cycle, except that two PSEN activations are skipped during each access to external data memory. PSEN is not activated during fetches from internal program memory. RESET A high level on this pin for two machine cycles while the oscillator is running resets the device. An internal diffused resistor to VSS permits power-on reset using only an external capacitor to VCC.
21
19
15
P2.0-P2.7
24-31
21-28
18-25
I/O
PSEN
32
29
26
O
RESET
10
9
4
I
Oct. 2000 Ver 3.1a
9
GMS90 Series
Pin Number Symbol ALE / PROG
PLCC44 PDIP40 MQFP44
Input/ Output O
Function The Address Latch Enable / Program pulse Output pulse for latching the low byte of the address during an access to external memory. In normal operation, ALE is emitted at a constant rate of 1/6 the oscillator frequency, and can be used for external timing or clocking. Note that one ALE pulse is skipped during each access to external data memory. This pin is also the program pulse input (PROG) during EPROM programming. In GMS9XC54/56/58: If desired, ALE operation can be disabled by setting bit 0 of SFR location 8EH. With this bit set, the pin is weakly pulled high. The ALE disable feature will be terminated by reset. Setting the ALE-disable bit has no affect if the microcontroller is in external execution mode.
33
30
27
EA / VPP
35
31
29
I
External Access Enable / Program Supply Voltage EA must be external held low to enable the device to fetch code from external program memory locations 0000H to FFFFH. If EA is held high, the device executes from internal program memory unless the program counter contains an address greater than its internal memory size. This pin also receives the 12.75V programming supply voltage (VPP) during EPROM programming. Note; however, that if any of the Lock bits are programmed, EA will be internally latched on reset.
P0.0-P0.7
36-43
32-39
30-37
I/O
Port 0 Port 0 is an 8-bit open-drain bidirectional I/O port. Port 0 pins that have 1s written to them float and can be used as high-impedance inputs. Port 0 is also the multiplexed low-order address and data bus during accesses to external program and data memory. In this application it uses strong internal pull-ups when emitting 1s. Port 0 also outputs the code bytes during program verification in the GMS97X5X. External pull-up resistors are required during program verification. Circuit ground potential Supply terminal for all operating modes No connection
VSS VCC N.C.
22 44 1,12 23,34
20 40 -
16 38 6,17 28,39
-
10
Oct. 2000 Ver 3.1a
GMS90 Series
FUNCTIONAL DESCRIPTION
The GMS90 series is fully compatible to the standard 8051 microcontroller family. It is compatible with the general 8051 family. While maintaining all architectural and operational characteristics of the general 8051 family.
Figure 1 shows a block diagram of the GMS90 series
XTAL1 XTAL2
RAM OSC & TIMING 128/256x8
ROM/EPROM 4K/8K/16K 24K/32K
RESET EA/VPP ALE/PROG PSEN
CPU Timer 0 Port 0 Timer 1 Port 1 Timer 2 Port 2 Interrupt Unit Port 3 Serial Channel Port 1 8-bit Digit. I/O Port 2 8-bit Digit. I/O Port 3 8-bit Digit. I/O Port 0 8-bit Digit. I/O
Figure 1. Block Diagram of the GMS90 series
Oct. 2000 Ver 3.1a
11
GMS90 Series
CPU
The GMS90 series is efficient both as a controller and as an arithmetic processor. It has extensive facilities for binary and BCD arithmetic and excels in its bit-handling capabilities. Efficient use of program memory results from an instruction set consisting of 44% one-byte, 41% two-byte, and 15% three-byte instructions. With a 12 MHz crystal, 58% of the instructions are executed in 1.0s (40MHz: 300ns). Special Function Register PSW
Bit No. Addr. D0H
MSB 7
LSB 6 5 4 3 2 1 0
CY
AC
F0
RS1 RS0 OV
F1
P
PSW
Bit
Function Carry Flag Auxiliary Carry Flag (for BCD operations) General Purpose Flag
CY AC F0 RS1 0 0 1 1 OV F1 P RS0 0 1 0 1
Register Bank select control bits Bank 0 selected, data address 00H - 07H Bank 1 selected, data address 08H - 0FH Bank 2 selected, data address 10H - 17H Bank 3 selected, data address 18H - 1FH Overflow Flag General Purpose Flag Parity Flag Set/cleared by hardware each instruction cycle to indicate an odd/even number of "one" bits in the accumulator, i.e. even parity.
Reset value of PSW is 00H.
12
Oct. 2000 Ver 3.1a
GMS90 Series
SPECIAL FUNCTION REGISTERS
All registers, except the program counter and the four general purpose register banks, reside in the special function register area. The 28 special function registers (SFR) include pointers and registers that provide an interface between the CPU and the other on-chip peripherals. There are also 128 directly addressable bits within the SFR area. All SFRs are listed in Table 1, Table 1, and Table 3. In Table 1 they are organized in numeric order of their addresses. In Table 2 they are organized in groups which refer to the functional blocks of the GMS90 series. Table 3 illustrates the contents of the SFRs.
Table 1. Special Function Registers in Numeric Order of their Addresses Address 80H 81H 82H 83H 84H 85H 86H 87H 88H 89H 8AH 8BH 8CH 8DH 8EH 3) 8FH Register P0 1) SP DPL DPH reserved reserved reserved PCON TCON 1) TMOD TL0 TL1 TH0 TH1 + 3) reserved Contents after Reset FFH 07H 00H 00H XXH 2) XXH 2) XXH 2) 0XX0000B 2) 00H 00H 00H 00H 00H 00H + 3) XXH 2) Address 90H 91H 92H 93H 94H 95H 96H 97H 98H 99H 9AH 9BH 9CH 9DH 9EH 9FH Register P1 1) reserved reserved reserved reserved reserved reserved reserved SCON 1) SBUF reserved reserved reserved reserved reserved reserved Contents after Reset FFH 00H XXH 2) XXH 2) XXH 2) XXH 2) XXH 2) XXH 2) 00H XXH 2) XXH 2) XXH 2) XXH 2) XXH 2) XXH 2) XXH 2)
1) Bit-addressable Special Function Register. 2) X means that the value is indeterminate and the location is reserved. 3) The GMS9XX54/56/58 have the AUXR0 register at address 8E H.
GMS9XX51/52 8EH reserved XXXXXXXXB2)
GMS9XX54/56/58 8EH AUXR0 XXXXXXX0B2)
Oct. 2000 Ver 3.1a
13
GMS90 Series
Table 1. Special Function Registers in Numeric Order of their Addresses (cont'd) Address A0H A1H A2H A3H A4H A5H A6H A7H A8H A9H AAH ABH ACH ADH AEH AFH B0H B1H B2H B3H B4H B5H B6H B7H B8H B9H BAH BBH BCH BDH BEH BFH C0H C1H C2H C3H C4H C5H C6H C7H Register P2 1) reserved reserved reserved reserved reserved reserved reserved IE 1) reserved reserved reserved reserved reserved reserved reserved P3 1) reserved reserved reserved reserved reserved reserved reserved IP 1) reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved Contents after Reset FFH XXH 2) XXH 2) XXH 2) XXH 2) XXH 2) XXH 2) XXH 2) 0X000000B 2) XXH 2) XXH 2) XXH 2) XXH 2) XXH 2) XXH 2) XXH 2) FFH XXH 2) XXH 2) XXH 2) XXH 2) XXH 2) XXH 2) XXH 2) XX000000B 2) XXH 2) XXH 2) XXH 2) XXH 2) XXH 2) XXH 2) XXH 2) XXH XXH 2) XXH 2) XXH 2) XXH 2) XXH 2) XXH 2) XXH 2) Address C8H C9H 3) CAH CBH CCH CDH CEH CFH D0H D1H D2H D3H D4H D5H D6H D7H D8H D9H DAH DBH DCH DDH DEH DFH E0H E1H E2H E3H E4H E5H E6H E7H E8H E9H EAH EBH ECH EDH EEH EFH Register T2CON 1) T2MOD RC2L RC2H TL2 TH2 reserved reserved PSW 1) reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved ACC 1) reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved Contents after Reset 00H + 3) 00H 00H 00H 00H XXH 2) XXH 2) 00H XXH 2) XXH 2) XXH 2) XXH 2) XXH 2) XXH 2) XXH 2) XXH 2) XXH 2) XXH 2) XXH 2) XXH 2) XXH 2) XXH 2) XXH 2) 00H XXH 2) XXH 2) XXH 2) XXH 2) XXH 2) XXH 2) XXH 2) XXH 2) XXH 2) XXH 2) XXH 2) XXH 2) XXH 2) XXH 2) XXH 2)
14
Oct. 2000 Ver 3.1a
GMS90 Series
Table 1. Special Function Registers in Numeric Order of their Addresses (cont'd) Address F0H F1H F2H F3H F4H F5H F6H F7H Register B 1) reserved reserved reserved reserved reserved reserved reserved Contents after Reset 00H XXH 2) XXH 2) XXH 2) XXH 2) XXH 2) XXH 2) XXH 2) Address F8H F9H FAH FBH FCH FDH FEH FFH Register reserved reserved reserved reserved reserved reserved reserved reserved Contents after Reset XXH 2) XXH 2) XXH 2) XXH 2) XXH 2) XXH 2) XXH 2) XXH 2)
1) Bit-addressable Special Function Register. 2) X means that the value is indeterminate and the location is reserved. 3) Address C9H is configured as below.
GMS9XX51/52 C9H reserved XXXXXXX0B
2)
GMS9XX54/56/58 C9H T2MOD XXXXXX00B2)
Oct. 2000 Ver 3.1a
15
GMS90 Series
Table 2. Special Function Registers - Functional Blocks Block CPU Symbol ACC B DPH DPL PSW SP IE IP P0 P1 P2 P3 PCON 3) SBUF SCON TCON TH0 TH1 TL0 TL1 TMOD T2CON T2MOD RC2H RC2L TH2 TL2 AUXR0 4) Saving PCON 3) Name Accumulator B-Register Data Pointer, High Byte Data Pointer, Low Byte Program Status Word Register Stack Pointer Interrupt Enable Register Interrupt Priority Register Port 0 Port 1 Port 2 Port 3 Power Control Register Serial Channel Buffer Reg. Serial Channel 0 Control Reg. Timer 0/1 Control Register Timer 0, High Byte Timer 1, High Byte Timer 0, Low Byte Timer 1, Low Byte Timer Mode Register Timer 2 Control Register Timer 2 Mode Register Timer 2 Reload Capture Reg., High Byte Timer 2 Reload Capture Reg., Low Byte Timer 2, High Byte Timer 2, Low Byte Aux. Register 0 Power Control Register Address E0H 1) F0H 1) 83H 82H D0H 1) 81H A8H 1) B8H 1) 80H 1) 90H 1) A0H 1) B0H 1) 87H 99H 98H 1) 88H 1) 8CH 8DH 8AH 8BH 89H C8H 1) C9H CBH CAH CDH CCH 8EH 87H Contents after Reset 00H 00H 00H 00H 00H 07H 0X000000B 2) XX000000B 2) FFH FFH FFH FFH 0XXX0000B 2) XXH 2) 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H XXXXXXX0B 2) 0XXX0000B 2)
Interrupt System
Ports
Serial Channels
Timer 0/ Timer 1
Timer 2
Power Modes
1) Bit-addressable Special Function register 2) X means that the value is indeterminate and the location is reserved 3) This special function register is listed repeatedly since some bit of it also belong to other functional blocks 4) The AUXR0 is in the GMS9XX54/56/58 only.
16
Oct. 2000 Ver 3.1a
GMS90 Series
Table 3. Contents of SFRs, SFRs in Numeric Order Address 80H 81H 82H 83H 87H 88H 89H 8AH 8BH 8CH 8DH 8EH 90H 98H 99H A0H A8H B0H B8H Register P0 SP DPL DPH PCON TCON TMOD TL0 TL1 TH0 TH1 AUXR0 P1 SCON SBUF P2 IE P3 IP PT2 PS PT1 PX1 PT0 PX0 EA ET2 ES ET1 EX1 ET0 EX0 SM0 SM1 SM2 REN TB8 RB8 TI RI A0 SM O D TF1 GATE TR1 C/T TF0 M1 TR0 MT GF1 IE1 GATE GF0 IT1 C/T PDE IE0 M1 IDLE IT0 M0
Bit 7 6 5 4 3 2 1 0
indicates resident in the GMS9XX54/56/58, not in 9XX51/52.
SFR bit and byte addressable SFR not bit addressable - : this bit location is reserved
Oct. 2000 Ver 3.1a
17
GMS90 Series
Table 3. Contents of SFRs, SFRs in Numeric Order (cont'd) Address C8H C9H CAH CBH CCH CDH D0H E0H F0H Register T2CON T2MOD RC2L RC2H TL2 TH2 PSW ACC B CY AC F0 RS1 RS0 OV F1 P
Bit 7 6 5 4 3 2 1 0
TF2 -
EXF2 -
RCLK -
TCLK -
EXEN 2 -
TR2 -
C/T2 T2O E
CP/RL2 DCEN
indicates resident in the GMS9XX54/56/58, not in 9XX51/52.
8EH
A0 A0 : ALE Signal Disable bit 0 : Enable ALE Signal (Generated ALE Signal) 1 : Disable ALE Signal (Not Generated ALE Signal)
C9H
T2OE
T2OE : Timer2 Output Enable bit 0 : Disable Timer2 Output 1 : Enable Timer2 Output
SFR bit and byte addressable SFR not bit addressable - : this bit location is reserved
18
Oct. 2000 Ver 3.1a
GMS90 Series
TIMER / COUNTER 0 AND 1
Timer/Counter 0 and 1 can be used in four operating modes as listed in Table 4:
Table 4. Timer/Counter 0 and 1 Operating Modes TMOD Mode Description
Gate C/T M1 M0 internal external (Max.)
Input Clock
0 1 2
8-bit timer/counter with a divide-by-32 prescaler 16-bit timer/counter 8-bit timer/counter with 8-bit auto-reload Timer/counter 0 used as one 8-bit timer/counter and one 8-bit timer Timer 1 stops
X X X
X X X
0 0 1
0 1 0
fOSC /(12x32) fOSC /12 fOSC /12
fOSC /(24x32) fOSC /24 fOSC /24
3
X
X
1
1
fOSC /12
fOSC /24
In the "timer" function (C/T = "0") the register is incremented every machine cycle. Therefore the count rate is fOSC/12. In the "counter" function the register is incremented in response to a 1-to-0 transition at its corresponding external input pin (P3.4/T0, P3.5/T1). Since it takes two machine cycles to detect a falling edge the max. count rate is fOSC/24. External inputs INT0 and INT1 (P3.2, P3.3) can be programmed to function as a gate to facilitate pulse width measurements. Figure 2 illustrates the input clock logic.
fOSC
/ 12 C/T TMOD 0
fOSC / 12
P3.4/T0 P3.5/T1 Max. fOSC/24 TR0 / 1 TCON Gate TMOD P3.2 / INT0 P3.3 / INT1 =1
Timer 0/1 Input Clock 1
&
1
Figure 2. Timer/Counter 0 and 1 Input Clock Logic
Oct. 2000 Ver 3.1a
19
GMS90 Series
TIMER 2
Timer 2 is a 16-bit timer/Counter with an up/down count feature. It can operate either as timer or as an event counter which is selected by bit C/T2 (T2CON.1). It has three operating modes as shown in Table 5.
Table 5. Timer/Counter 2 Operating Modes
T2CON T2MO T2CON D TR2 DCEN EXEN2
Mode
RCLK or CP/RL2 TCLK
P1.1/ T2EX X 0 1 X X X
Input Clock Remarks
internal external (P1.0/T2)
16-bit AutoReload
0 0 0 0
0 0 0 0 1
1 1 1 1 1
0 0 1 1 X
0 1 X X 0
reload upon overflow reload trigger (falling edge) Down counting Up counting 16 bit Timer/ Counter (only up-counting) capture TH2,TL2 RC2H,RC2L no overflow interrupt request (TF2) extra external interrupt ("Timer 2") Timer 2 stops
fOSC / 12
Max. fOSC /24
16-bit Capture
0
fOSC / 12
0 Baud Rate Generator 1
1 X
1 1
X X
1 0
Max. fOSC / 24
fOSC / 12
1 Off Note: = X
X X
1 0
X X
1 X
Max. fOSC / 24
-
-
falling edge
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GMS90 Series
SERIAL INTERFACE (USART)
The serial port is full duplex and can operate in four modes (one synchronous mode, three asynchronous modes) as illustrated in Table 6. The possible baud rates can be calculated using the formulas given in Table 7.
Table 6. USART Operating Modes SCON Mode SM0 0 0 SM1 0 Baudrate Description Serial data enters and exits through RxD. TxD outputs the shift clock. 8-bit are transmitted/received (LSB first) 8-bit UART 10 bits are transmitted (through TxD) or received (RxD) 9-bit UART 11 bits are transmitted (TxD) or received (RxD) 9-bit UART Like mode 2 except the variable baud rate
f OSC ----------12
1
0
1
Timer 1/2 overflow rate
2 3
1 1
0 1
f OSC f OSC ----------- or ----------32 64
Timer 1/2 overflow rate
Table 7. Formulas for Calculating Baud rates Baud Rate derived from Interface Mode 0 Oscillator 2 Baudrate
f OSC ----------12 2 ----------------- x f OSC 64 2 ----------------- x ( Timer 1 overflow ) 32
SMOD f OSC 2 ----------------- x ------------------------------------------------32 12 x [ 256 - ( TH1 ) ] SMOD SMOD
Timer 1 (16-bit timer) (8-bit timer with 8-bit auto reload)
1,3
1,3
Timer 2
1,3
f OSC --------------------------------------------------------------------------------32 x [ 65536 - ( RC2H, RC2L ) ]
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GMS90 Series
INTERRUPT SYSTEM
The GMS90 series provides 5 (4K bytes ROM version) or 6 (above 8K bytes ROM version) interrupt sources with two priority levels. Figure 3 gives a general overview of the interrupt sources and illustrates the request and control flags.
High Priority Timer 0 Overflow TF0 TCON.5 ET0 IE.1 PT0 IP.1 Low Priority
Timer 1 Overflow
TF1 TCON.7 ET1 IE.3 PT1 IP.3
Timer 2 Overflow P1.1/ T2EX EXEN2 T2CON.3 UART
TF2 T2CON.7 EXF2 T2CON.6 RI SCON.0 TI SCON.1
1 ET2 IE.5 1 PT2 IP.5
ES IE.4
PS IP.4
P3.2/ INT0 IT0 TCON.0 P3.3/ INT1 IT1 TCON.2
IE0 TCON.1 EX0 IE.0 PX0 IP.0
IE1 TCON.3 EX1 IE.2 EA IE.7 PX1 IP.2
: Low level triggered : Falling edge triggered
Figure 3. Interrupt Request Sources
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Oct. 2000 Ver 3.1a
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Table 8. Interrupt Sources and their Corresponding Interrupt Vectors Source (Request Flags) RESET IE0 TF0 IE1 TF1 RI + TI TF2 + EXF2 Vectors RESET External interrupt 0 Timer 0 interrupt External interrupt 1 Timer 1 interrupt Serial port interrupt Timer 2 interrupt 0000H 0003H 000BH 0013H 001BH 0023H 002BH Vector Address
A low-priority interrupt can itself be interrupted by a high-priority interrupt, but not by another low priority interrupt. A high-priority interrupt cannot be interrupted by any other interrupt source.
If two requests of different priority level are received simultaneously, the request of higher priority is serviced. If requests of the same priority are received simultaneously, an internal polling sequence determines which request is serviced. Thus within each priority level there is a second priority structure determined by the polling sequence as shown in Table 9.
Table 9. Interrupt Priority-Within-Level Interrupt Source External Interrupt 0 Timer 0 Interrupt External Interrupt 1 Timer 1 Interrupt Serial Channel Timer 2 Interrupt IE0 TF0 IE1 TF1 RI + TI TF2 + EXF2 Priority High Low
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GMS90 Series
Power Saving Modes
Two power down modes are available, the Idle Mode and Power Down Mode. The bits PDE and IDLE of the register PCON select the Power Down mode or the Idle mode, respectively. If the Power Down mode and the Idle mode are set at the same time, the Power Down mode takes precedence. Table 10 gives a general overview of the power saving modes.
Table 10. Power Saving Modes Overview Entering Instruction Example ORL PCON, #01H
Mode Idle mode
Leaving by - Enabled interrupt - Hardware Reset
Remarks CPU is gated off CPU status registers maintain their data. Peripherals are active Oscillator is stopped, contents of onchip RAM and SFR's are maintained (leaving Power Down Mode means redefinition of SFR contents).
Power-Down mode
ORL PCON, #02H
Hardware Reset
In the Power Down mode of operation, VCC can be reduced to minimize power consumption. It must be ensured, however, that VCC is not reduced before the Power Down mode is invoked, and that VCC is restored to its normal operating level, before the Power Down mode is terminated. The reset signal that terminates the Power Down mode also restarts the oscillator. The reset should not be activated before VCC is restored to its normal operating level and must be held active long enough to allow the oscillator to restart and stabilize (similar to power-on reset).
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Oct. 2000 Ver 3.1a
GMS90 Series
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
Ambient temperature under bias (TA)...................................................................................... -40 to + 85 C Storage temperature (TST)...................................................................................................... -65 to + 150 C Voltage on VCC pins with respect to ground (VSS) ................................................................. -0.5V to 6.5V Voltage on any pin with respect to ground (VSS) ..........................................................-0.5V to VCC + 0.5V Input current on any pin during overload condition............................................................-15mA to +15mA Absolute sum of all input currents during overload condition ...........................................................|100mA| Power dissipation ....................................................................................................................................1.5W
Note: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage of the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for longer periods may affect device reliability. During overload conditions (VIN > VCC or VIN < VSS) the Voltage on VCC pins with respect to ground (VSS) must not exceed the values defined by the absolute maximum ratings.
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GMS90 Series
DC Characteristics
DC Characteristics for GMS90C31/32, GMS90C51/52/54/56/58 VCC= 5V + 10%, -15%; VSS=0V; TA= 0C to 70C
Parameter Input low voltage (except EA, RESET) Input low voltage (EA) Input low voltage (RESET) Input high voltage (except XTAL1, EA, RESET) Input high voltage to XTAL1 Input high voltage to EA, RESET Output low voltage (ports 1, 2, 3) Output low voltage (port 0, ALE, PSEN) Output high voltage (ports 1, 2, 3) Output high voltage (port 0 in external bus mode, ALE, PSEN) Logic 0 input current (ports 1, 2, 3) Logical 1-to-0 transition current (ports 1, 2, 3) Input leakage current (port 0, EA) Pin capacitance Power supply current: Active mode, 12MHz 3) Idle mode, 12MHz 3) Active mode, 24 MHz 3) Idle mode, 24MHz 3) Active mode, 40 MHz 3) Idle mode, 40 MHz 3) Power Down Mode 3) Symbol VIL VIL1 VIL2 VIH VIH1 VIH2 VOL VOL1 VOH VOH1 IIL ITL ILI CIO ICC ICC ICC ICC ICC ICC IPD Limit Values Min. -0.5 -0.5 -0.5 0.2VCC + 0.9 0.7VCC 0.6VCC 2.4 0.9VCC 2.4 0.9VCC -10 -65 Max. 0.2VCC - 0.1 0.2VCC - 0.3 0.2VCC + 0.1 VCC + 0.5 VCC + 0.5 VCC + 0.5 0.45 0.45 Unit V V V V V V V V V Test Conditions IOL= 1.6mA 1) IOL= 3.2mA 1) IOH= -80A IOH= -10A IOH= -800A 2) IOH= -80A 2) VIN= 0.45V VIN= 2.0V 0.45 < VIN < VCC fC= 1MHz TA= 25C VCC= 5V 4) VCC= 5V 5) VCC= 5V 4) VCC= 5V 5) VCC= 5V 4) VCC= 5V 5) VCC= 5V 6)
-50 -650 1 10
V A A A pF
-
21 4.8 36.2 8.2 58.5 12.5 50
mA mA mA mA mA mA A
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Oct. 2000 Ver 3.1a
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1) Capacitive loading on ports 0 and 2 may cause spurious noise pulses to be superimposed on the VOL of ALE and port 3. The noise is due to external bus capacitance discharging into the port 0 and port 2 pins when these pins make 1-to-0 transitions during bus operation. In the worst case (capacitive loading: > 50pF at 3.3V, > 100pF at 5V), the noise pulse on ALE line may exceed 0.8V. In such cases it may be desirable to qualify ALE with a schmitt-trigger, or use an address latch with a schmitt-trigger strobe input. 2) Capacitive loading on ports 0 and 2 may cause the VOH on ALE and PSEN to momentarily fall below the 0.9VCC specification when the address lines are stabilizing. 3) ICC Max at other frequencies is given by: active mode: ICC = 1.27 x fOSC + 5.73 idle mode: ICC = 0.28 x fOSC + 1.45 (except OTP devices) where fOSC is the oscillator frequency in MHz. I CC values are given in mA and measured at VCC = 5V. 4) ICC (active mode) is measured with: XTAL1 driven with tCLCH, tCHCL = 5ns, VIL = VSS + 0.5V, VIH = VCC - 0.5V; XTAL2 = N.C.; EA = Port0 = RESET = VCC; all other pins are disconnected. ICC would be slightly higher if a crystal oscillator is used (appr. 1mA). 5) ICC (Idle mode) is measured with all output pins disconnected and with all peripherals disabled; XTAL1 driven with tCLCH, tCHCL = 5ns, VIL = VSS + 0.5V, VIH = VCC - 0.5V; XTAL2 = N.C.; RESET = EA = VSS; Port0 = VCC; all other pins are disconnected; 6) IPD (Power Down Mode) is measured under following conditions: EA = Port0 = VCC; RESET = VSS; XTAL2 = N.C.; XTAL1 = VSS; all other pins are disconnected.
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GMS90 Series
DC Characteristics for GMS97C51/52/54/56/58 (H) VCC= 5V + 10%, -15%; VSS=0V; TA= 0C to 70C
Parameter Input low voltage (except EA, RESET) Input low voltage (EA) Input low voltage (RESET) Input high voltage (except XTAL1, EA, RESET) Input high voltage to XTAL1 Input high voltage to EA, RESET Output low voltage (ports 1, 2, 3) Output low voltage (port 0, ALE, PSEN) Output high voltage (ports 1, 2, 3) Output high voltage (port 0 in external bus mode, ALE, PSEN) Logic 0 input current (ports 1, 2, 3) Logical 1-to-0 transition current (ports 1, 2, 3) Input leakage current (port 0, EA) Pin capacitance Power supply current: Active mode, 12MHz 3) Idle mode, 12MHz 3) Active mode, 24 MHz 3) Idle mode, 24MHz 3) Active mode, 33 MHz 3) Idle mode, 33 MHz 3) Power Down Mode 3) Symbol VIL VIL1 VIL2 VIH VIH1 VIH2 VOL VOL1 VOH VOH1 IIL ITL ILI CIO ICC ICC ICC ICC ICC ICC IPD Limit Values Min. -0.5 -0.5 -0.5 0.2VCC + 0.9 0.7VCC 0.6VCC 2.4 0.9VCC 2.4 0.9VCC -10 -65 Max. 0.2VCC - 0.1 0.2VCC - 0.3 0.2VCC + 0.1 VCC + 0.5 VCC + 0.5 VCC + 0.5 0.45 0.45 Unit V V V V V V V V V Test Conditions IOL= 1.6mA 1) IOL= 3.2mA 1) IOH= -80A IOH= -10A IOH= -800A 2) IOH= -80A 2) VIN= 0.45V VIN= 2.0V 0.45 < VIN < VCC fC= 1MHz TA= 25C VCC= 5V 4) VCC= 5V 5) VCC= 5V 4) VCC= 5V 5) VCC= 5V 4) VCC= 5V 5) VCC= 5V 6)
-50 -650 1 10
V A A A pF
-
21 4.8 36.2 8.2 45 10 50
mA mA mA mA mA mA A
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GMS90 Series
DC Characteristics for GMS90L31/32, GMS90L51/52/54/56/58 VCC= 3.3V + 0.3V, -0.6V; VSS=0V; TA= 0C to 70C
Limit Values Parameter Input low voltage Input high voltage Output low voltage (ports 1, 2, 3) Output low voltage (port 0, ALE, PSEN) Output high voltage (ports 1, 2, 3) Output high voltage (port 0 in external bus mode, ALE, PSEN) Logic 0 input current (ports 1, 2, 3) Logical 1-to-0 transition current (ports 1, 2, 3) Input leakage current (port 0, EA) Pin capacitance Power supply current: Active mode, 16 MHz 3) Idle mode, 16MHz 3) Power Down Mode 3) Symbol Min. VIL VIH VOL -0.5 2.0 Max. 0.8 VCC + 0.5 0.45 0.30 0.45 0.30 V V V IOL= 1.6mA 1) IOL= 100A 1) IOL= 3.2mA 1) IOL= 200A 1) IOH= -20A IOH= -10A IOH= -800A 2) IOH= -80A 2) VIN= 0.45V VIN= 2.0V 0.45 < VIN < VCC fC= 1MHz TA= 25C VCC= 3.6V 4) VCC= 2.6V 5) VCC=2~ 5.5V 6) Unit Test Conditions
VOL1 VOH
2.0 0.9VCC 2.0 0.9VCC -1 -25 -
V
V
VOH1
-
V
IIL ITL ILI CIO
-50 -250 1 10
A A A pF
ICC ICC IPD
-
15 5 10
mA mA A
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GMS90 Series
DC Characteristics for GMS97L51/52/54/56/58 VCC= 3.3V + 0.3V, -0.6V; VSS=0V; TA= 0C to 70C
Limit Values Parameter Input low voltage Input high voltage Output low voltage (ports 1, 2, 3) Output low voltage (port 0, ALE, PSEN) Output high voltage (ports 1, 2, 3) Output high voltage (port 0 in external bus mode, ALE, PSEN) Logic 0 input current (ports 1, 2, 3) Logical 1-to-0 transition current (ports 1, 2, 3) Input leakage current (port 0, EA) Pin capacitance Power supply current: Active mode, 12MHz 3) Idle mode, 12MHz 3) Power Down Mode 3) Symbol Min. VIL VIH VOL -0.5 2.0 max. 0.8 VCC + 0.5 0.45 0.30 0.45 0.30 V V V IOL= 1.6mA 1) IOL= 100A 1) IOL= 3.2mA 1) IOL= 200A 1) IOH= -20A IOH= -10A IOH= -800A 2) IOH= -80A 2) VIN= 0.45V VIN= 2.0V 0.45 < VIN < VCC fC= 1MHz TA= 25C VCC= 3.6V 4) VCC= 2.6V 5) VCC=2~ 5.5V 6) Unit Test Conditions
VOL1 VOH
2.0 0.9VCC 2.0 0.9VCC -1 -25 -
V
V
VOH1
-
V
IIL ITL ILI CIO
-50 -250 1 10
A A A pF
ICC ICC IPD
-
15 5 10
mA mA A
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Oct. 2000 Ver 3.1a
GMS90 Series
AC Characteristics
Explanation of the AC Symbols Each timing symbol has 5 characters. The first character is always a `t' (stand for time). The other characters, depending on their positions, stand for the name of a signal or the logical status of that signal. The following is a list of all the characters and what they stand for.
A: Address C: Clock D: Input Data H: Logic level HIGH I: Instruction (program memory contents) L: Logic level LOW, or ALE P: PSEN Q: Output Data R: RD signal T: Time V: Valid W: WR signal X: No longer a valid logic level Z: Float For example, tAVLL = Time from Address Valid to ALE Low tLLPL = Time from ALE Low to PSEN Low
AC Characteristics for GMS90 series (12MHz version)
VCC= 5V : VCC= 3.3V : Variable clock : VCC= 5V + 10%, - 15%; VSS= 0V; TA= 0C to 70C (CL for port 0. ALE and PSEN outputs = 100pF; CL for all other outputs = 80pF) VCC= 3.3V + 0.3V, - 0.6V; VSS= 0V; TA= 0C to 70C (CL for port 0. ALE and PSEN outputs = 50pF; CL for all other outputs = 50pF) Vcc = 5V : 1/tCLCL = 3.5 MHz to 12 MHz Vcc = 3.3V : 1/tCLCL = 1 MHz to 12 MHz
External Program Memory Characteristics
12 MHz Oscillator Parameter Symbol Min. ALE pulse width Address setup to ALE Address hold after ALE ALE low to valid instruction in ALE to PSEN PSEN pulse width PSEN to valid instruction in Input instruction hold after PSEN Input instruction float after PSEN Address valid after PSEN tLHLL tAVLL tLLAX tLLIV tLLPL tPLPH tPLIV tPXIX tPXIZ tPXAV 127 43 30 58 215 0 75 Max. 233 150 63 Variable Oscillator 1/tCLCL = 3.5 to 12MHz Min. 2tCLCL-40 tCLCL-40 tCLCL-53 tCLCL-25 3tCLCL-35 0 tCLCL-8 Max. 4tCLCL-100 3tCLCL-100 tCLCL-20 ns ns ns ns ns ns ns ns ns ns Unit
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GMS90 Series
12 MHz Oscillator Parameter Symbol Min. Address to valid instruction in Address float to PSEN tAVIV tAZPL 0 Max. 302 -
Variable Oscillator 1/tCLCL = 3.5 to 12MHz Min. 0 Max. 5tCLCL-115 -
Unit
ns ns
Interfacing the GMS90 series to devices with float times up to 75 ns is permissible. This limited bus contention will not cause
any damage to port 0 Drivers.
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Oct. 2000 Ver 3.1a
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AC Characteristics for GMS90 series (12MHz) External Data Memory Characteristics
12 MHz Oscillator Parameter Symbol Min. RD pulse width WR pulse width Address hold after ALE RD to valid data in Data hold after RD Data float after RD ALE to valid data in Address to valid data in ALE to WR or RD Address valid to WR or RD WR or RD high to ALE high Data valid to WR transition Data setup before WR Data hold after WR Address float after RD tRLRH tWLWH tLLAX2 tRLDV tRHDX tRHDZ tLLDV tAVDV tLLWL tAVWL tWHLH tQVWX tQVWH tWHQX tRLAZ 400 400 53 0 200 203 43 33 433 33 Max. 252 97 517 585 300 123 0 Variable Oscillator 1/tCLCL = 3.5 to 12MHz Min. 6tCLCL-100 6tCLCL-100 tCLCL-30 0 3tCLCL-50 4tCLCL-130 tCLCL-40 tCLCL-50 7tCLCL-150 tCLCL-50 Max. 5tCLCL-165 2tCLCL-70 8tCLCL-150 9tCLCL-165 3tCLCL+50 tCLCL+40 0 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Unit
Advance Information (12MHz) External Clock Drive
Parameter Symbol Variable Oscillator (Freq. = 3.5 to 12MHz) Min. Oscillator period (VCC=5V) Oscillator period (VCC=3.3V) High time Low time Rise time Fall time tCLCL tCLCL tCHCX tCLCX tCLCH tCHCL 83.3 83.3 20 20 Max. 285.7 1 tCLCL - tCLCX tCLCL - tCHCX 20 20 ns ns ns ns ns Unit
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GMS90 Series
AC Characteristics for GMS90 series (16MHz version) VCC= 3.3V + 0.3V, -0.6V; VSS= 0V; TA= 0C to 70C
(CL for port 0. ALE and PSEN outputs = 50pF; CL for all other outputs = 50pF)
External Program Memory Characteristics
16 MHz Oscillator Parameter Symbol Min. ALE pulse width Address setup to ALE Address hold after ALE ALE low to valid instruction in ALE to PSEN PSEN pulse width PSEN to valid instruction in Input instruction hold after PSEN Input instruction float after PSEN Address valid after PSEN Address to valid instruction in Address float to PSEN tLHLL tAVLL tLLAX tLLIV tLLPL tPLPH tPLIV tPXIX tPXIZ tPXAV tAVIV tAZPL 85 23 23 38 153 0 55 0 Max. 150 88 43 198 Variable Oscillator 1/tCLCL = 3.5 to 16MHz Min. 2tCLCL-40 tCLCL-40 tCLCL-40 tCLCL-25 3tCLCL-35 0 tCLCL-8 0 Max. 4tCLCL-100 3tCLCL-100 tCLCL-20 5tCLCL-115 ns ns ns ns ns ns ns ns ns ns ns ns Unit
Interfacing the GMS90 series to devices with float times up to 35 ns is permissible. This limited bus contention will not cause
any damage to port 0 Drivers.
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Oct. 2000 Ver 3.1a
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AC Characteristics for GMS90 series (16MHz) External Data Memory Characteristics
16 MHz Oscillator Parameter Symbol Min. RD pulse width WR pulse width Address hold after ALE RD to valid data in Data hold after RD Data float after RD ALE to valid data in Address to valid data in ALE to WR or RD Address valid to WR or RD WR or RD high to ALE high Data valid to WR transition Data setup before WR Data hold after WR Address float after RD tRLRH tWLWH tLLAX2 tRLDV tRHDX tRHDZ tLLDV tAVDV tLLWL tAVWL tWHLH tQVWX tQVWH tWHQX tRLAZ 275 275 23 0 138 120 28 13 288 23 Max. 183 75 350 398 238 97 0 Variable Oscillator 1/tCLCL = 3.5 to 16MHz Min. 6tCLCL-100 6tCLCL-100 tCLCL-40 0 3tCLCL-50 4tCLCL-130 tCLCL-35 tCLCL-50 7tCLCL-150 tCLCL-40 Max. 5tCLCL-130 2tCLCL-50 8tCLCL-150 9tCLCL-165 3tCLCL+50 tCLCL+35 0 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Unit
Advance Information (16MHz) External Clock Drive
Parameter Symbol Variable Oscillator (Freq. = 3.5 to 16MHz) Min. Oscillator period High time Low time Rise time Fall time tCLCL tCHCX tCLCX tCLCH tCHCL 62.5 17 17 Max. 285.7 tCLCL - tCLCX tCLCL - tCHCX 17 17 ns ns ns ns ns Unit
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GMS90 Series
AC Characteristics for GMS90 series (24MHz version) VCC= 5V + 10%, -15%; VSS= 0V; TA= 0C to 70C
(CL for port 0. ALE and PSEN outputs = 100pF; CL for all other outputs = 80pF)
External Program Memory Characteristics
24 MHz Oscillator Parameter Symbol Min. ALE pulse width Address setup to ALE Address hold after ALE ALE low to valid instruction in ALE to PSEN PSEN pulse width PSEN to valid instruction in Input instruction hold after PSEN Input instruction float after PSEN Address valid after PSEN Address to valid instruction in Address float to PSEN tLHLL tAVLL tLLAX tLLIV tLLPL tPLPH tPLIV tPXIX tPXIZ tPXAV tAVIV tAZPL 43 17 17 22 95 0 37 0 Max. 80 60 32 148 Variable Oscillator 1/tCLCL = 3.5 to 24MHz Min. 2tCLCL-40 tCLCL-25 tCLCL-25 tCLCL-20 3tCLCL-30 0 tCLCL-5 0 Max. 4tCLCL-87 3tCLCL-65 tCLCL-10 5tCLCL-60 ns ns ns ns ns ns ns ns ns ns ns ns Unit
Interfacing the GMS90 series to devices with float times up to 35 ns is permissible. This limited bus contention will not cause
any damage to port 0 Drivers.
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Oct. 2000 Ver 3.1a
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AC Characteristics for GMS90 series (24MHz) External Data Memory Characteristics
24 MHz Oscillator Parameter Symbol Min. RD pulse width WR pulse width Address hold after ALE RD to valid data in Data hold after RD Data float after RD ALE to valid data in Address to valid data in ALE to WR or RD Address valid to WR or RD WR or RD high to ALE high Data valid to WR transition Data setup before WR Data hold after WR Address float after RD tRLRH tWLWH tLLAX2 tRLDV tRHDX tRHDZ tLLDV tAVDV tLLWL tAVWL tWHLH tQVWX tQVWH tWHQX tRLAZ 180 180 15 0 75 67 17 5 170 15 Max. 118 63 200 220 175 67 0 Variable Oscillator 1/tCLCL = 3.5 to 24MHz Min. 6tCLCL-70 6tCLCL-70 tCLCL-27 0 3tCLCL-50 4tCLCL-97 tCLCL-25 tCLCL-37 7tCLCL-122 tCLCL-27 Max. 5tCLCL-90 2tCLCL-20 8tCLCL-133 9tCLCL-155 3tCLCL+50 tCLCL+25 0 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Unit
Advance Information (24MHz) External Clock Drive
Parameter Symbol Variable Oscillator (Freq. = 3.5 to 24MHz) Min. Oscillator period High time Low time Rise time Fall time tCLCL tCHCX tCLCX tCLCH tCHCL 41.7 12 12 Max. 285.7 tCLCL - tCLCX tCLCL - tCHCX 12 12 ns ns ns ns ns Unit
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GMS90 Series
AC Characteristics for GMS90 series (33MHz version) VCC= 5V + 10%, -15%; VSS= 0V; TA= 0C to 70C
(CL for port 0. ALE and PSEN outputs = 100pF; CL for all other outputs = 80pF)
External Program Memory Characteristics
33 MHz Oscillator Parameter Symbol Min. ALE pulse width Address setup to ALE Address hold after ALE ALE low to valid instruction in ALE to PSEN PSEN pulse width PSEN to valid instruction in Input instruction hold after PSEN Input instruction float after PSEN Address valid after PSEN Address to valid instruction in Address float to PSEN tLHLL tAVLL tLLAX tLLIV tLLPL tPLPH tPLIV tPXIX tPXIZ tPXAV tAVIV tAZPL 40 10 10 15 80 0 25 0 Max. 56 35 20 91 Variable Oscillator 1/tCLCL = 3.5 to 33MHz Min. 2tCLCL-20 tCLCL-20 tCLCL-20 tCLCL-15 3tCLCL-20 0 tCLCL-5 0 Max. 4tCLCL-65 3tCLCL-55 tCLCL-10 5tCLCL-60 ns ns ns ns ns ns ns ns ns ns ns ns Unit
Interfacing the GMS90 series to devices with float times up to 35 ns is permissible. This limited bus contention will not cause
any damage to port 0 Drivers.
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Oct. 2000 Ver 3.1a
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AC Characteristics for GMS90 series (33MHz) External Data Memory Characteristics
33 MHz Oscillator Parameter Symbol Min. RD pulse width WR pulse width Address hold after ALE RD to valid data in Data hold after RD Data float after RD ALE to valid data in Address to valid data in ALE to WR or RD Address valid to WR or RD WR or RD high to ALE high Data valid to WR transition Data setup before WR Data hold after WR Address float after RD tRLRH tWLWH tLLAX2 tRLDV tRHDX tRHDZ tLLDV tAVDV tLLWL tAVWL tWHLH tQVWX tQVWH tWHQX tRLAZ 132 132 10 0 71 66 10 5 142 10 Max. 81 46 153 183 111 40 0 Variable Oscillator 1/tCLCL = 3.5 to 33MHz Min. 6tCLCL-50 6tCLCL-50 tCLCL-20 0 3tCLCL-20 4tCLCL-55 tCLCL-20 tCLCL-25 7tCLCL-70 tCLCL-20 Max. 5tCLCL-70 2tCLCL-15 8tCLCL-90 9tCLCL-90 3tCLCL+20 tCLCL+20 0 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Unit
Advance Information (33MHz) External Clock Drive
Parameter Symbol Variable Oscillator (Freq. = 3.5 to 24MHz) Min. Oscillator period High time Low time Rise time Fall time tCLCL tCHCX tCLCX tCLCH tCHCL 30.3 11.5 11.5 Max. 285.7 tCLCL - tCLCX tCLCL - tCHCX 5 5 ns ns ns ns ns Unit
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GMS90 Series
AC Characteristics for GMS90 series (40MHz version) VCC= 5V + 10%, - 15%; VSS= 0V; TA= 0C to 70C
(CL for port 0. ALE and PSEN outputs = 100pF; CL for all other outputs = 80pF)
External Program Memory Characteristics
40 MHz Oscillator Parameter Symbol Min. ALE pulse width Address setup to ALE Address hold after ALE ALE low to valid instruction in ALE to PSEN PSEN pulse width PSEN to valid instruction in Input instruction hold after PSEN Input instruction float after PSEN Address valid after PSEN Address to valid instruction in Address float to PSEN tLHLL tAVLL tLLAX tLLIV tLLPL tPLPH tPLIV tPXIX tPXIZ tPXAV tAVIV tAZPL 35 10 10 10 60 0 20 5 Max. 55 25 15 65 Variable Oscillator 1/tCLCL = 3.5 to 40MHz Min. 2tCLCL-15 tCLCL-15 tCLCL-15 tCLCL-15 3tCLCL-15 0 tCLCL-5 5 Max. 4tCLCL-45 3tCLCL-50 tCLCL-10 5tCLCL-60 ns ns ns ns ns ns ns ns ns ns ns ns Unit
Interfacing the GMS90 series to devices with float times up to 20 ns is permissible. This limited bus contention will not cause
any damage to port 0 Drivers.
40
Oct. 2000 Ver 3.1a
GMS90 Series
AC Characteristics for GMS90 series (40MHz) External Data Memory Characteristics
at 40 MHz Clock Parameter Symbol Min. RD pulse width WR pulse width Address hold after ALE RD to valid data in Data hold after RD Data float after RD ALE to valid data in Address to valid data in ALE to WR or RD Address valid to WR or RD WR or RD high to ALE high Data valid to WR transition Data setup before WR Data hold after WR Address float after RD tRLRH tWLWH tLLAX2 tRLDV tRHDX tRHDZ tLLDV tAVDV tLLWL tAVWL tWHLH tQVWX tQVWH tWHQX tRLAZ 120 120 10 0 60 70 10 5 125 5 Max. 75 38 150 150 90 40 0 Variable Clock 1/tCLCL = 3.5 to 40MHz Min. 6tCLCL-30 6tCLCL-30 tCLCL-15 0 3tCLCL-15 4tCLCL-30 tCLCL-15 tCLCL-20 7tCLCL-50 tCLCL-20 Max. 5tCLCL-50 2tCLCL-12 8tCLCL-50 9tCLCL-75 3tCLCL+15 tCLCL+15 0 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Unit
Advance Information (40MHz) External Clock Drive
Parameter Symbol Variable Oscillator (Freq. = 3.5 to 40MHz) Min. Oscillator period High time Low time Rise time Fall time tCLCL tCHCX tCLCX tCLCH tCHCL 25 10 10 Max. 285.7 tCLCL - tCLCX tCLCL - tCHCX 10 10 ns ns ns ns ns Unit
Oct. 2000 Ver 3.1a
41
GMS90 Series
tLHLL
ALE
tLLPL tAVLL tLLIV tPLIV tPLPH
PSEN
tAZPL tLLAX tPXAV tPXIZ tPXIX INSTR. IN tAVIV A0-A7
PORT 0
A0-A7
PORT 2
A8-A15
A8-A15
Figure 4. External Program Memory Read Cycle
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Oct. 2000 Ver 3.1a
GMS90 Series
ALE
tLHLL tWHLH
PSEN
tLLWL
tLLDV tRLRH
RD
tAVLL tLLAX2 tRLDV tRLAZ tRHDX
DATA IN A0-A7 from PCL INSTR. IN
tRHDZ
PORT 0
A0-A7 from RI or DPL
tAVWL tAVDV
PORT 2
P2.0-P2.7 or A8-A15 from DPH
A8-A15 from PCH
Figure 5. External Data Memory Read Cycle
ALE
tLHLL tWHLH
PSEN
tLLWL tWLWH
WR
tAVLL tQVWX tLLAX2
A0-A7 from RI or DPL
tWHQX tQVWH
DATA OUT A0-A7 from PCL INSTR. IN
PORT 0
tAVWL
PORT 2
P2.0-P2.7 or A8-A15 from DPH
A8-A15 from PCH
Figure 6. External Data Memory Write Cycle
Oct. 2000 Ver 3.1a
43
GMS90 Series
VCC-0.5V
0.2VCC + 0.9 Test Points
0.45V
0.2VCC - 0.1
AC Inputs during testing are driven at VCC-0.5V for a logic `1' and 0.45V for a logic `0'. Timing measurements are made a VIHmin for a logic `1' and VILmax for a logic `0'.
Figure 7. AC Testing: Input, Output Waveforms
VLOAD + 0.1 VLOAD VLOAD - 0.1 Timing Reference Points 0.2VCC - 0.1
VOH - 0.1
VOL + 0.1
For timing purposes a port pin is no longer floating when a 100mV change from load voltage occurs and begins to float when a 100mV change from the loaded V OH / VOL level occurs. IOL / IOH 20mA.
Figure 8. Float Waveforms
tCLCL VCC-0.5V 0.7 VCC 0.2 VCC -0.1 tCHCX tCHCL tCLCH tCLCX
0.45V
Figure 9. External Clock Cycle
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Oct. 2000 Ver 3.1a
GMS90 Series
OSCILLATOR CIRCUIT
CRYSTAL OSCILLATOR MODE
DRIVING FROM EXTERNAL SOURCE
C2 XTAL2 P-LCC-44/Pin 20 P-DIP-40/Pin 18 M-QFP-44/Pin 14 C1 XTAL1 P-LCC-44/Pin 21 P-DIP-40/Pin 19 M-QFP-44/Pin 15
N.C.
XTAL2 P-LCC-44/Pin 20 P-DIP-40/Pin 18 M-QFP-44/Pin 14
External Oscillator Signal
XTAL1 P-LCC-44/Pin 21 P-DIP-40/Pin 19 M-QFP-44/Pin 15
C1, C2 = 30pF 10pF for Crystals For Ceramic Resonators, contact resonator manufacturer.
Figure 10. Recommended Oscillator Circuits
Oscillation circuit is designed to be used either with a ceramic resonator or crystal oscillator. Since each crystal and ceramic resonator have their own characteristics, the user should consult the crystal manufacturer for appropriate values of external components.
Oct. 2000 Ver 3.1a
45
GMS90 Series
OTP ROM Verification Characteristics
ROM Verification Mode 1
Limit Values Parameter Address to valid data ENABLE to valid data Data float after ENABLE Oscillator frequency Symbol Min. tAVQV tCLCL tEHQZ 1/tCLCL 0 4 Max. 48tCLCL 48tCLCL 48tCLCL 6 MHz ns Unit
P1.0-P1.7 P2.0-P2.4
Address tAVQV Data Out tELQV
PORT 0
tEHQZ
P2.7 ENABLE
Address: P1.0-P1.7 = A0-A7 P2.0-P2.5 = A8-A13 P3.4 = A14 Data: P0.0-P0.7 = D0-D7
Input: P2.6-P2.7, PSEN = VSS ALE = VIH EA, RESET = VIH2
Figure 11. OTP ROM Verification Mode 1
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Oct. 2000 Ver 3.1a
GMS90 Series
EPROM CHARACTERISTICS
The GMS97C5X, 97L5X are programmed by using a modified Quick-Pulse ProgrammingTM algorithm. It differs from older methods in the value used for VPP (programming supply voltage) and in the width and number of the ALE/PROG pulses. The GMS97C5X, 97L5X contains two signature bytes that can be read and used by an EPROM programming system to identify the device. The signature bytes identify the device as an manufactured by HME. Table 11 shows the logic levels for reading the signature byte, and for programming the program memory, the encryption table, and the security bits. The circuit configuration and waveforms for quick-pulse programming are shown in Figure 12 and Figure 13. Figure 14 show the circuit configuration for normal program memory verification. Reading the Signature Bytes : The GMS97X51/52 signature bytes in locations 030H and 031H, the GMS97X54/56/58 signature bytes in locations 05EH and 07CH. To read these bytes follow the procedure for EPROM verify, except that P3.6 and P3.7 need to be pulled to a logic low. The values are:
Device GMS97X51 GMS97X52 GMS97X54 GMS97X56 GMS97X58 Location 30H 31H 30H 31H 5EH 7CH 5EH 7CH 5EH 7CH Contents E0H 73H E0H 71H E0H 54H E0H 56H E0H 58H Remarks Manufacturer ID Device ID Manufacturer ID Device ID Manufacturer ID Device ID Manufacturer ID Device ID Manufacturer ID Device ID
Quick-pulse programming The setup for microcontroller quick-pulse programming is shown in Figure 13. Note that the GMS97C5X, 97L5X is running with a 4 to 6MHz oscillator. The reason the oscillator needs to be running is that the device is executing internal address and program data transfers. The address of the EPROM location to be programmed is applied to ports 1 and 2, as shown in Figure 12. The code byte to be programmed into that location is applied to port 0, RST, PSEN and pins of port 2 and 3 in Table 11 are held at the "Program Code Data" levels indicated in Table 11. The ALE/PROG is pulsed low 25 times(10 times for 97X54/56/58) as shown Figure 13. To program the encryption table, repeat the 25 pulses (10 pulses for 97X54/56/58) programming sequence for addresses 0 through 1FH(3FH for 97X54/56/58), using the "Program Encryption Table" levels. Do not forget that after the encryption table is programmed, verification cycles will produce only encrypted data. To program the security bits, repeat the 25 pulses (10 pulses for 97X54/56/58) programming sequence using the "Pgm Security Bit" levels after one security bit is programmed, further programming of the code memory and
Oct. 2000 Ver 3.1a
47
GMS90 Series
encryption table is disabled. However, the other security bit can still be programmed. Note that the EA/VPP pin must not be allowed to go above the maximum specified VPP level for any amount of time. Even a narrow glitch above that voltage can cause permanent damage to the device. The VPP source should be well regulated and free glitches and overshoot.
+5V VCC P0 A8-A13 A14 1 1 1 4~6MHz XTAL1 VSS P2.0 -P2.5 P3.4 RST P3.6 P3.7 XTAL2 PSEN P2.7 P2.6 0 1 1 EA/VPP +12.75V PROGRAM DATA
A0-A7
P1
ALE/PROG
+NOTE
NOTE: GMS97X51/52:
100s x 25 pulses to GND
GMS97X54/56/58: 100s x 10 pulses to GND Figure 12. Programming Configuration
Program Verification If security bit 2 has not been programmed, the on-chip program memory can be read out for program verification. The address of the program memory location to be read is applied to ports 1 and 2 as shown in Figure 15. The other pins are held at the "Verify Code Data" levels indicated in Table 11. The contents of the address location will be emitted on port 0 for this operation. If the encryption table has been programmed, the data presented at port 0 will be the exclusive NOR of the program byte with one of the encryption bytes. The user will have to know the encryption table contents in order to correctly decode the verification data. The encryption table itself cannot be read out.
48
Oct. 2000 Ver 3.1a
GMS90 Series
Program Memory Lock Bits The two-level Program Lock system consists of 2 Lock bits and a 32-byte (64-byte for GMS97X54/ 56/58) Encryption Array which are used to protect the program memory against software piracy. Encryption Array:
Lock Bit Protection Modes Mode 1 2 3 LB1 U P P LB2 U U P Protection Type No program lock features Further programming of the EPROM is disabled Same as mode 2, also verify is
disabled Within the EPROM array are 32 bytes (64 bytes for GMS97X54/56/58) of Encryption Array that U: unprogrammed, P: programmed are initially unprogrammed (all 1s). Every time that a byte is addressed during a verify, address lines are used to select a byte of the Encryption array. This byte is then exclusive-NORed (XNOR) with the code byte, creating an Encrypted Verify byte.
The algorithm, with the array in the unprogrammed state (all 1s), will return the code in its original, unmodified form, It is recommended that whenever the Encryption Array is used, at least one of the Lock Bits be programmed as well. Program / Verify algorithms Any algorithm in agreement with the conditions listed in Table 11, and which satisfies the timing specifications is suitable.
Table 11. EPROM programming modes MODE Read Signature Program Code Data Verify Code Data Program encryption table Program security bit 1 Program security bit 2 RST 1 1 1 1 1 1 PSEN 0 0 0 0 0 0 ALE/ PROG 1 0 1 0 0 0 EA/ VPP 1 VPP 1 VPP VPP VPP P2.7 0 1 0 1 1 1 P2.6 0 0 0 0 1 1 P3.7 0 1 1 1 1 0 P3.6 0 1 1 0 1 0
Notes: 1. "0" = Valid low for that pin, "1" = valid high for that pin. 2. VPP = 12.75V 0.25V 3. VCC = 5V 10% during programming and verification. 4. ALE/PROG receives 25 (10 for GMS97X54/56/58) programming pulses while V PP is held at 12.75V. Each programming pulse is low for 100us ( 10us) and high for a minimum of 10s.
Oct. 2000 Ver 3.1a
49
GMS90 Series
In the GMS97X51/52
ALE/PROG
25 PULSES
Min. 10s 100s 10 Enlarged View 100s 10
In the GMS97X54/56/58
ALE/PROG
10 PULSES
Figure 13. PROG Waveform
+5V VCC A0-A7 A8-A13 A14 1 1 1 4~6MHz XTAL1 VSS P1 P2.0 -P2.5 P3.4 EA/VPP RST P3.6 P3.7 XTAL2 ALE/PROG PSEN P2.7 P2.6 1 0 0 1 1 P0 10k PROGRAM DATA
Figure 14. Program Verification
50
Oct. 2000 Ver 3.1a
GMS90 Series
EPROM Programming and Verification Characteristics TA= 21C to 27C, VCC= 5V + 10%, - 15%; VSS=0V;
Limit Values Parameter Programming supply voltage Programming supply current Oscillator frequency Address setup to PROG low Address hold after PROG Data setup to PROG Data hold after PROG P2.7 (ENABLE) high to VPP VPP setup to PROG VPP hold after PROG PROG width Address to data valid ENABLE low to data valid Data float after ENABLE PROG high to PROG low Symbol Min. VPP IPP 1/tCLCL tAVGL tGHAX tDVGL tGHDX tEHSH tSHGL tGHSL tGLGL tAVQV tELQV tEHQZ tGHGL 12.5 4 48tCLCL 48tCLCL 48tCLCL 48tCLCL 48tCLCL 10 10 90 0 10 Max. 13.0 50 6 110 48tCLCL 48tCLCL 48tCLCL V mA MHz s s s s Unit
PROGRAMMING
VERIFICATION ADDRESS
P1.0-P1.7 P2.0-P2.5 P3.4 PORT 0 tDVGL tAVGL ALE/PROG
~~ ~~
ADDRESS
tAVQV
~~ ~~
DATA IN
DATA OUT
25 or 10 PULSES
tGHDX tGHAX
~ ~
tSHGL
tGHGL VPP
t G LG L
EA/VPP TTL HIGH tEHSH
tGHSL
~ ~
TTL HIGH tELQV TTL HIGH tEHQZ
~ ~
P2.7 (ENABLE)
Figure 15. EPROM Programming and Verification
Oct. 2000 Ver 3.1a
51
GMS90 Series
Plastic Package P-LCC-44 (Plastic Leaded Chip-Carrier) 44PLCC UNIT: INCH
0.695 0.685 0.656 0.650 min. 0.020
0.032 0.026
0.695 0.685
0.656 0.650
0.021 0.013
0.050 BSC
0.012 0.0075
0.120 0.090 0.180 0.165
52
0.630 0.590
Oct. 2000 Ver 3.1a
GMS90 Series
Plastic Package P-DIP-40 (Plastic Dual in-Line Package)
40DIP
UNIT: INCH
2.075 2.045 0.200 max.
min. 0.015
0.600 BSC 0.550 0.530
0.140 0.120
0.022 0.015
0.065 0.045
0.100 BSC
0-15
0.012 0.008
Oct. 2000 Ver 3.1a
53
GMS90 Series
Plastic Package P-MPQF-44 (Plastic Metric Quad Flat Package) 44MQFP
13.45 12.95 10.10 9.90
UNIT: MM
13.45 12.95
10.10 9.90
2.10 1.95
SEE DETAIL "A" 0.25 0.10
0-7
2.35 max. 0.45 0.30
1.03 0.73 1.60 REF
0.80 BSC
DETAIL "A"
54
Oct. 2000 Ver 3.1a
0.23 0.13
MASK ORDER & VERIFICATION SHEET
GMS90X5X-GB
Customer should write inside thick line box.
1. Customer Information
Company Name Application
YYYY MM DD
2. Device Information
ROM size 4K 8K 16K 24K 40PDIP 3V Package 44MQFP 44PLCC 5V Vol. / Freq. 12MHz 24MHz 40MHz 12MHz 16MHz
Order Date
Tel: Name & Signature:
Fax:
32K
ROM Protection Mask Data File Name: ( Check Sum: Internet
ROM: 4K,8K ROM: 16,24,32K
Without
Normal
Super
.HEX)
3. Marking Specification 40PDIP or 44PLCC HYNIX GMS90 5 -GB YYW W KOREA (c)SIEMENS '92
Chollian
Hitel
)
(Please check mark into
44MQFP HYNIX 90 5 -GB YYW W KOREA (c)SIEM ENS '92
C: 5V L: 3V
RO M size 1: 4K 2: 8K 4: 16K 6: 24K 8: 32K
Custom er's part num ber
4. Delivery Schedule
Date Customer Sample Risk Order
YYYY MM DD
Quantity
Hynix Confirmation
pcs pcs
This box is written after "5.Verification".
YYYY
MM
DD
5. ROM Code Verification Verification D ate:
YYYY MM DD
YYYY
MM
DD
Approval Date:
I agree w ith your verification data and confirm you to m ake m ask set.
P lease confirm our verification data.
Check Sum: Tel: Name & Signature: Fax:
Tel: Name & Signature:
Fax:
////////Hynix semiconductor ////////

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